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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Synthesis results and different behavior

I made an SPI interface circuit, but the SCLK output is always 'H' and it doesn't work. It would be helpful if you could give me some hint to solve it. The survey results are as follows. 1) MOSI...
  • sstrell's avatar
    sstrell
    3 years ago

    1) Yes. There are many VHDL attributes like this. Just googled this: https://redirect.cs.umbc.edu/portal/help/VHDL/attribute.html

    2) Not sure what you mean here, but if your clock is not coded correctly, then nothing is going to work correctly because it will never get to the if checks.

    3) rising_edge is part of std_logic, so as long as you're using that library, it will work and is recommended.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

The code can be compiled correctly. However, I recommend reviewing your design in the RTL viewer to ensure that it has the desired functionality.


Could you please share your testbench and the simulation result with me? I would like to understand what is meant by "[SCLK output is always 'H']."


Best Regards,

Richard Tan


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