Forum Discussion
Occasional ContributorSynthesis results and different behavior
1) Yes. There are many VHDL attributes like this. Just googled this: https://redirect.cs.umbc.edu/portal/help/VHDL/attribute.html
2) Not sure what you mean here, but if your clock is not coded correctly, then nothing is going to work correctly because it will never get to the if checks.
3) rising_edge is part of std_logic, so as long as you're using that library, it will work and is recommended.
Super Contributor1) Yes. There are many VHDL attributes like this. Just googled this: https://redirect.cs.umbc.edu/portal/help/VHDL/attribute.html
2) Not sure what you mean here, but if your clock is not coded correctly, then nothing is going to work correctly because it will never get to the if checks.
3) rising_edge is part of std_logic, so as long as you're using that library, it will work and is recommended.
Yamada1Thank you for answering.
I understand that "CLK'event" (no spaces) is the way to specify attributes.
As you pointed out, I confirmed the operation by synthesizing with the space removed from "SYS_CLK' event" on line 156 and synthesizing with "rising_edge (SYS_CLK)" changed, but there is no improvement It didn't (changed only parts that weren't working correctly to see the difference).
Will lines 152 to 165 not work properly due to other "SYS_CLK' events" (with spaces) in PLL_SPI.vhd?
I'm sorry to trouble you, but it would be helpful if you could teach me.
