Forum Discussion
Occasional ContributorSynthesis results and different behavior
1) Yes. There are many VHDL attributes like this. Just googled this: https://redirect.cs.umbc.edu/portal/help/VHDL/attribute.html
2) Not sure what you mean here, but if your clock is not coded correctly, then nothing is going to work correctly because it will never get to the if checks.
3) rising_edge is part of std_logic, so as long as you're using that library, it will work and is recommended.
Super ContributorRight off the bat from your code, you have your clock if-checks in all processes to "SYS_CLK' event" when it should be "SYS_CLK'event" (no space). Better would be to use rising_edge(SYS_CLK). This could be your whole problem because you would never get to the DATA_SHIFT_FLAG check for s_sclk to go low.
Occasional ContributorThank you for answering.
Thank you for pointing out about the synchronization circuit.
Sorry to trouble you, but it would be helpful if you could teach us the following points.
1) Is "CLK'event" (without spaces) a rule of VHDL grammar? Or is it because it affects interpretation during synthesis of Quartus Prime?
2) According to your answer, the reason is that the processing from line 157 onwards is not performed because the rise of CLK has not occurred. It seems that it is not working itself, but is that recognition correct? 3) In your answer, the description of "rising_edge(SYS_CLK)" is recommended, but is it possible in VHDL1993?
Sorry for the inconvenience, but thank you in advance.
