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Altera_Forum's avatar
Altera_Forum
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14 years ago

Synthesis of ROM & Synthesis Attributes

Hello,

My question is regarding how Quartus handles attributes versus setting options in Quartus itself. For the ROM code shown below, using just the attribute directive, it will not synthesize into the embedded memory of the Cyclone IV device. However, when I use the advance settings in Quartus for "synthesize any ROM size", then it does place the lookup table into embedded memory. So is this to mean that a synthesis directive placed into HDL code is ignored if the overlying Quartus rules don't see fit? Or do I have a problem with my synthesis directive?

Any comments much appreciated.

Thanks, James

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ROM_12x60 is
     port(
                ADDR      : in std_logic_vector(5 downto 0);  
                CLK        : in std_logic;  
                q           : out std_logic_vector(11 downto 0)  
         );
end ROM_12x60; 
    architecture RTL of ROM_12x60 is
    attribute romstyle : string;
    attribute romstyle of rtl : architecture is "M9K";
    signal addr_int : integer range 0 to 2**6;
    begin
    addr_int <= to_integer(unsigned(addr));
    Main: process(clk) begin
         if rising_edge(clk) then
            case addr_int is
                 when 0      => q <= "000000000000"; 
                 when 1      => q <= "000000100100"; 
                 when 2      => q <= "000001000111"; 
                 when 3      => q <= "000001101011"; 
                 when 4      => q <= "000010001111"; 
                 when 5      => q <= "000010110010"; 
                 when 6      => q <= "000011010110"; 
                 when 7      => q <= "000011111010"; 
                 when 8      => q <= "000100011101"; 
                 when 9      => q <= "000101000000"; 
                 when 10      => q <= "000101100100"; 
                 when 11      => q <= "000110000111"; 
                 when 12      => q <= "000110101010"; 
                 when 13      => q <= "000111001101"; 
                 when 14      => q <= "000111101111"; 
                 when 15      => q <= "001000010010"; 
                 when 16      => q <= "001000110101"; 
                 when 17      => q <= "001001010111"; 
                 when 18      => q <= "001001111001"; 
                 when 19      => q <= "001010011011"; 
                 when 20      => q <= "001010111100"; 
                 when 21      => q <= "001011011110"; 
                 when 22      => q <= "001011111111"; 
                 when 23      => q <= "001100100000"; 
                 when 24      => q <= "001101000001"; 
                 when 25      => q <= "001101100010"; 
                 when 26      => q <= "001110000010"; 
                 when 27      => q <= "001110100010"; 
                 when 28      => q <= "001111000001"; 
                 when 29      => q <= "001111100001"; 
                 when 30      => q <= "010000000000"; 
                 when 31      => q <= "010000011111"; 
                 when 32      => q <= "010000111101"; 
                 when 33      => q <= "010001011011"; 
                 when 34      => q <= "010001111001"; 
                 when 35      => q <= "010010010111"; 
                 when 36      => q <= "010010110100"; 
                 when 37      => q <= "010011010001"; 
                 when 38      => q <= "010011101101"; 
                 when 39      => q <= "010100001001"; 
                 when 40      => q <= "010100100100"; 
                 when 41      => q <= "010101000000"; 
                 when 42      => q <= "010101011010"; 
                 when 43      => q <= "010101110101"; 
                 when 44      => q <= "010110001111"; 
                 when 45      => q <= "010110101000"; 
                 when 46      => q <= "010111000001"; 
                 when 47      => q <= "010111011010"; 
                 when 48      => q <= "010111110010"; 
                 when 49      => q <= "011000001010"; 
                 when 50      => q <= "011000100001"; 
                 when 51      => q <= "011000111000"; 
                 when 52      => q <= "011001001110"; 
                 when 53      => q <= "011001100100"; 
                 when 54      => q <= "011001111001"; 
                 when 55      => q <= "011010001110"; 
                 when 56      => q <= "011010100010"; 
                 when 57      => q <= "011010110110"; 
                 when 58      => q <= "011011001001"; 
                 when 59      => q <= "011011011011"; 
                 when 60      => q <= "011011101110"; 
                 when 61      => q <= "011011111111"; 
                 when others      => q <= "000000000000";
             end case;
         end if;
    end process Main;
end RTL;
--END Module

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    According to the Quartus help, the attribute should be associated with the signal. Connecting it to the architecture will be ignored:

    --- Quote Start ---

    To use the romstyle synthesis attribute, first declare the synthesis attribute with a string type. Then associate the romstyle synthesis attribute with a Signal or Variable Declaration that represents an inferred ROM with an attribute specification. Specify the synthesis attribute value as "logic", "M512", "M4K", "M9K", "M144K", "MLAB", or "M-RAM", depending on the type of memory block that you want the Quartus II software to use when you implement the inferred ROM. If you associate the synthesis attribute with any other VHDL object, or if you specify an illegal value, the Quartus II software ignores that synthesis attribute.

    --- Quote End ---

    So associate the attribute with "q" and see if it makes a difference.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I did add the attribute with q as the signal, and this did work. I removed the Quartus settings for "synthesize any ROM size" and after compilation the ROM was placed into embedded memory. This is helpful because when the source VHDL is made with these attributes the downstream configuration options in Quartus don't have to be set, which is what I was aiming for. James

    The modified VHDL is shown below:

    
    library IEEE;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    entity ROM_12x60 is
         port(
                    ADDR      : in std_logic_vector(5 downto 0);  
                    CLK      : in std_logic;  
                    q      : out std_logic_vector(11 downto 0)  
             );
    end ROM_12x60; 
        architecture RTL of ROM_12x60 is
        attribute romstyle : string;
         attribute romstyle of q : signal is "M9K";
        signal addr_int : integer range 0 to 2**6;
        begin
        addr_int <= to_integer(unsigned(addr));
        Main: process(clk) begin
             if rising_edge(clk) then
                case addr_int is
                     when 0      => q <= "000000000000"; 
                     when 1      => q <= "000000100100"; 
                     when 2      => q <= "000001000111"; 
                     when 3      => q <= "000001101011"; 
                     when 4      => q <= "000010001111"; 
                     when 5      => q <= "000010110010"; 
                     when 6      => q <= "000011010110"; 
                     when 7      => q <= "000011111010"; 
                     when 8      => q <= "000100011101"; 
                     when 9      => q <= "000101000000"; 
                     when 10      => q <= "000101100100"; 
                     when 11      => q <= "000110000111"; 
                     when 12      => q <= "000110101010"; 
                     when 13      => q <= "000111001101"; 
                     when 14      => q <= "000111101111"; 
                     when 15      => q <= "001000010010"; 
                     when 16      => q <= "001000110101"; 
                     when 17      => q <= "001001010111"; 
                     when 18      => q <= "001001111001"; 
                     when 19      => q <= "001010011011"; 
                     when 20      => q <= "001010111100"; 
                     when 21      => q <= "001011011110"; 
                     when 22      => q <= "001011111111"; 
                     when 23      => q <= "001100100000"; 
                     when 24      => q <= "001101000001"; 
                     when 25      => q <= "001101100010"; 
                     when 26      => q <= "001110000010"; 
                     when 27      => q <= "001110100010"; 
                     when 28      => q <= "001111000001"; 
                     when 29      => q <= "001111100001"; 
                     when 30      => q <= "010000000000"; 
                     when 31      => q <= "010000011111"; 
                     when 32      => q <= "010000111101"; 
                     when 33      => q <= "010001011011"; 
                     when 34      => q <= "010001111001"; 
                     when 35      => q <= "010010010111"; 
                     when 36      => q <= "010010110100"; 
                     when 37      => q <= "010011010001"; 
                     when 38      => q <= "010011101101"; 
                     when 39      => q <= "010100001001"; 
                     when 40      => q <= "010100100100"; 
                     when 41      => q <= "010101000000"; 
                     when 42      => q <= "010101011010"; 
                     when 43      => q <= "010101110101"; 
                     when 44      => q <= "010110001111"; 
                     when 45      => q <= "010110101000"; 
                     when 46      => q <= "010111000001"; 
                     when 47      => q <= "010111011010"; 
                     when 48      => q <= "010111110010"; 
                     when 49      => q <= "011000001010"; 
                     when 50      => q <= "011000100001"; 
                     when 51      => q <= "011000111000"; 
                     when 52      => q <= "011001001110"; 
                     when 53      => q <= "011001100100"; 
                     when 54      => q <= "011001111001"; 
                     when 55      => q <= "011010001110"; 
                     when 56      => q <= "011010100010"; 
                     when 57      => q <= "011010110110"; 
                     when 58      => q <= "011011001001"; 
                     when 59      => q <= "011011011011"; 
                     when 60      => q <= "011011101110"; 
                     when 61      => q <= "011011111111"; 
                     when others      => q <= "000000000000";
                 end case;
             end if;
        end process Main;
    end RTL;