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Honored Contributor
Honored Contributorsyncronous clocks
This may seem a like a stupid question, but I am new to Altera FPGA's. When using a PLL to generate syncronous clocks, lets say a base clock and a base clock multipled by 2 for example, can I assume ...
Altera_ForumHonored Contributor
Honored ContributorMy understanding is that if you set multicycle path on "enable signal" then quartus understands that is meant for all registers that use this enable as enable...so it is not applied to enable register itself because it is not enabled by itself.
