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Honored Contributor
Honored Contributorsyncronous clocks
This may seem a like a stupid question, but I am new to Altera FPGA's. When using a PLL to generate syncronous clocks, lets say a base clock and a base clock multipled by 2 for example, can I assume ...
Altera_ForumHonored Contributor
Honored ContributorTimeQuest will do proper analysis between these PLL outputs though, and sending logic between these clocks is done all the time. So there's nothing wrong with what you're doing.
