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Honored Contributor
Honored Contributorsyncronous clocks
This may seem a like a stupid question, but I am new to Altera FPGA's. When using a PLL to generate syncronous clocks, lets say a base clock and a base clock multipled by 2 for example, can I assume ...
Altera_ForumHonored Contributor
Honored ContributorBasically you should always sample your data at the right speed. So you can't feed data from slow clk to fast clk unless you control the rate through enable signal. As you said, an enable signal is better than multiple clk system if that is feasible.
