syncronous clocks

Care to elaborate on that. I know the phase of the clocks should be closely aligned, my question was if they are close enough so I can transfer data from one clock domain to the other without metastable and race condition problems, and if the Quartus software will consider the skew between the clocks in the timing analyzer. If not then the prudent design would be to clock all registers with the faster clock and use a clock enable on the registers that I want to clock every other clock.