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Honored Contributor
Honored Contributorsyncronous clocks
This may seem a like a stupid question, but I am new to Altera FPGA's. When using a PLL to generate syncronous clocks, lets say a base clock and a base clock multipled by 2 for example, can I assume ...
Altera_ForumHonored Contributor
Honored Contributorreading your post again, it seems you got some confusion about the question.
There are two issues, phase and use of clks. They are separate...
