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Altera_Forum's avatar
Altera_Forum
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15 years ago

synchronous process on both edges

Dear All, is is possible to create a synchronous process reacting on both clock edges? Is it synthesized? Or I have to use PLL to go for twice higher clock frequency and use only rising_edge? ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi,

no, a process that is sensitive to both edges cannot be synthesized, at least not in a FPGA.

The general solution would be to use a PLL.

Of course, in some application cases you can get the job done by using two different processes on the two clock edges. The most relevant case is DDR I/O.