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Altera_Forum's avatar
Altera_Forum
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15 years ago

Synchronization problem in PWM generation

I am using the DE2 board to generate a 20 kHz PWM signal. The duty ratio is constant 20%. The device is implemented by verilog. My method is to use DE2 board to generate a 20 kHz * 1000 = 20 MHz cloc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You should use a synchronization chain as described in the Quartus Software Handbook and logic design text books. 

always @(posedge clk)
begin
  pwm_trig_s0 <= pwm_trig;
  pwm_trig_s1 <= pwm_trig_s0;
  if (pwm_trig_s1==1) //control the slope of the triangle wave.
    b=-1;
  else
    b=1;
//....
end