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Altera_Forum
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15 years ago

Synchronization problem in PWM generation

I am using the DE2 board to generate a 20 kHz PWM signal. The duty ratio is constant 20%. The device is implemented by verilog. My method is to use DE2 board to generate a 20 kHz * 1000 = 20 MHz cloc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Oh, I am sorry. The code is wrong. This is correct:

if (pwm_trig==1) //control the slope of the triangle wave.

b=-1;

if (pwm_trig==0)//triangle wave is rising when synchronization signal is 0

b=1;

The pwm_trig is the 20kHz synchronization signal. It comes from a master dsp controller. What is the meaning of “the required setup and hold time”? Due to the structure of our system, I have to use the external synchronization signal (20kHz) and internal clk signal (20 MHz). Is there any solution?

Thank you!