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Altera_Forum's avatar
Altera_Forum
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15 years ago

Synchronization problem in PWM generation

I am using the DE2 board to generate a 20 kHz PWM signal. The duty ratio is constant 20%. The device is implemented by verilog. My method is to use DE2 board to generate a 20 kHz * 1000 = 20 MHz cloc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I guess, pwm_trig is unrelated to clk, at least not guaranteed to meet the required setup and hold time? Then it's not correct to use it, as you do in your logic, it has to be synchronized to clk by two flip-flops.

I assume, this is not the real code. 

if (pwm_trig==1) //control the slope of the triangle wave.
b=-1;
if (pwm_trig==1)
b=1