New Contributor
Super ContributorSynchronous resets are recommended over asynch if possible.
I guess I don't understand the issue. If clock enable is needed, then it must be enabled for a synch reset to work. If you don't need clock enable, then don't use it and synch reset will work.
New ContributorI'm glad to hear sync resets are recommended. And I understand that I need to assert CE for the sync reset to work.
My concern is the extra logic that it takes. With AMD, I don't need to assure the clock enable is asserted. Assert sync reset and the flip-flop will reset on the next rising edge of the clock.
Say I have a module with a sync reset input. The clock enable on each flip flop is used to register the data. I would expect that the flip-flops in the module are going need various signals for the CE but only the single reset. But with the Intel FF priority, I will need to do:
local_ce_0 <= sync_reset or ce_0
local_ce_1 <= sync_reset or ce_1
...
local_ce_x <= sync_reset or ce_x
Maybe with being new to Intel FPGAs I'm not thinking about it correctly. But it seems that it adds to the source code and the hardware required.
Another issue for those of you with experience porting designs between the two vendors -- if you're using sync resets do you rewrite the code to account for the different priority?
