Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorStuck on Fast QSPI
I have a 100 MHz clock generated by an internal PLL in a Cyclone IV design, and I would like to read from a QSPI peripheral at 100MHz (i.e. 400Mbit per second). That seems like it should be po...
Altera_ForumHonored Contributor
Honored ContributorThe Tco of the QSPI part (6ns) is longer than the time from a falling edge to a rising edge (5ns). Why would moving to the 5ns window instead of the 10ns window help? Additionally, won’t that break the data output paths to the QSPI part since those share the same clock as the data input paths?
TimeQuest is also telling me that adding a DDIO block to the clock path increases the FPGA’s clock output delay. Do you have any examples of what you are describing?
