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Honored Contributor
Honored ContributorStuck on Fast QSPI
I have a 100 MHz clock generated by an internal PLL in a Cyclone IV design, and I would like to read from a QSPI peripheral at 100MHz (i.e. 400Mbit per second). That seems like it should be po...
Altera_ForumHonored Contributor
Honored ContributorIn your case I would invert output clock FLASH_SCLK by using Altera altddio_out. This way you can avoid clocking FLASH logic inside FPGA from negative edge. In this case you have to change generated clock constrains for CLK_FLASH and define false path on output clock port FLASH_SCLK. Let me know if you need some help with timing constrains.
