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Altera_Forum
Honored Contributor
Honored ContributorStuck on Fast QSPI
I have a 100 MHz clock generated by an internal PLL in a Cyclone IV design, and I would like to read from a QSPI peripheral at 100MHz (i.e. 400Mbit per second). That seems like it should be po...
Altera_ForumHonored Contributor
Honored ContributorSure, I can do even better. This zip file contains a complete project with everything stripped out except the flash support. It also includes a simple self-checking ModelSim Altera testbench if you run “run_sim.do” in the sim folder.
One thing that may be confusing is that the flash logic clocks data in on falling edges. Since data is clocked out on falling edges, that allows a full period to deal with Tco delays instead of only half a period.
