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Altera_Forum
Honored Contributor
Honored ContributorStuck on Fast QSPI
I have a 100 MHz clock generated by an internal PLL in a Cyclone IV design, and I would like to read from a QSPI peripheral at 100MHz (i.e. 400Mbit per second). That seems like it should be po...
Altera_ForumHonored Contributor
Honored ContributorHi,
can you provide your design archive or at least .sdc file? It would be easier to understand your design and I will try to help you.
