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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

Stratix10 PCIe clock structure issue

Hello everyone， I am using quartus Pro 22.3 , device ( stratix10 1SX110HN2F43I2VG ) , IP core ( L-Tile and H-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express 22.2.0, GEN 3X4 125Mhz. ug...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
10 months ago

Hi allen18,


My apology for the delayed response.

When you used the crystal oscillator, did the PCIe link up successfully?


Yes, when using the separate clock architecture, users must set the Slot Clock Configuration to "off" in the Quartus IP Parameter. Could you also confirm that the RP side of the link has disabled the spread spectrum?


Could you please ensure that the reference clock (AT33, AT34) has 100 MHz ±300 ppm according to the PCI Express Card Electromechanical Specification Revision 2.0. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration.


Besides, where is the other refclk, and what are the pin assignments for refclk 0 and refclk 1 in both cases?


Thanks.

Best Regards,

Ven


allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Hi ventt,

I am currently unable to determine whether the issue is caused by my local environment, such as clock quality. Can you try running an Example Design in your environment ? Select PCIe avmm as the IP and set the slot clock configuration to OFF.

Thanks.