Stratix10 Dx P-tile PCIe flow control

hi, thanks for your help. I'm try to build own pcie adptor base on s10dx P-tile ST IP. I get some confuse for flow control in P-tile st ip user guide

when i set TLP pkg to st ip, usually I need check where opposite end has enough credit to accept my pkg. but i don't understand how the st ip describe about flow control:

For example, if the remote Receiver advertises an initial Non-Posted Header (NPH) FC credit of 0xFFFF, after it receives a MRd request, the NPH FC credits value increments by 1 and rolls over to 0x0000. The tx_cdts_limit_tdm_idx_o[2:0] signals determine the traffic type(From user guide

).

would please tell me there is additional logic to check flow control? if yes, how i get credits for opposite end form st ip user guide description, if not, the st ip core would check it self? and pull down ready signals for delay transmission?