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GDeXi's avatar
GDeXi
Icon for Occasional Contributor rankOccasional Contributor
6 years ago
Solved

Stratix10 Dx P-tile PCIe flow control

hi, thanks for your help. I'm try to build own pcie adptor base on s10dx P-tile ST IP. I get some confuse for flow control in P-tile st ip user guide when i set TLP pkg to st ip, usually I n...
  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    5 years ago

    Hi ,

    Sorry for my confusion answer

    Kindly find the inline answers.

    would please tell me there is additional logic to check flow control?

    >>No ,The ip have the capability to verify the flow control

Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi ,

The TX will work as same as RX Flow control. I am copying the descript from the ug for your reference.

The RX flow control interface provides information on the application's available RX
buffer space to the PCIe Hard IP in a time-division multiplexing (TDM) manner. It
reports the space available in number of TLPs.
The RX flow control interface is optional and disabled by default in the IP GUI. If
disabled, it indicates that there is no limit in the application RX buffer space

Pag no: 52

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf

  • GDeXi's avatar
    GDeXi
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Sorry, I do not understand what your mean, could you please description it more clearly

    • Rahul_S_Intel1's avatar
      Rahul_S_Intel1
      Icon for Frequent Contributor rankFrequent Contributor
      5 years ago

      Hi ,

      Sorry for my confusion answer

      Kindly find the inline answers.

      would please tell me there is additional logic to check flow control?

      >>No ,The ip have the capability to verify the flow control