Occasional Contributor
Hi ,
Sorry for my confusion answer
Kindly find the inline answers.
would please tell me there is additional logic to check flow control?
>>No ,The ip have the capability to verify the flow control
Frequent ContributorHi ,
The TX will work as same as RX Flow control. I am copying the descript from the ug for your reference.
The RX flow control interface provides information on the application's available RX
buffer space to the PCIe Hard IP in a time-division multiplexing (TDM) manner. It
reports the space available in number of TLPs.
The RX flow control interface is optional and disabled by default in the IP GUI. If
disabled, it indicates that there is no limit in the application RX buffer space
Pag no: 52
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf
Occasional ContributorSorry, I do not understand what your mean, could you please description it more clearly
Frequent ContributorHi ,
Sorry for my confusion answer
Kindly find the inline answers.
would please tell me there is additional logic to check flow control?
>>No ,The ip have the capability to verify the flow control
