Stratix V PLL question

From this article: http://www.altera.com/devices/fpga/stratix-fpgas/stratix-v/overview/fpll/stxv-fpll.html?gsa_pos=2&wt.oss_r=1&wt.oss=delta sigma

as shown in figure 2, the client frequency information in the aggregate data stream is used to control the delta-sigma modulators in the fplls, allowing for precise synthesis of the required client line rate frequencies.

So, we should give to fPLL some information, that is used by delta-sigma modulators to generate required frequency.

The question is, what information should we give and how it will be used to produce frequency that we need and what will be the quality of the clock.