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Altera_Forum
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11 years ago

Stratix V PLL Location Congestion

Hi, I'm working on a design based around a Stratix V GS D6 FPGA. In the design there are two UniPHY memory controllers being implemented on the bottom of the chip. These two controllers will ru...
Altera_Forum's avatar
Altera_Forum
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11 years ago

It answers the question of why both PLLs can't be in the centre, but I am still stuck with the timing errors on the RLDRAM (no matter what frequency I set the memory clock to, I get exactly the same setup/hold violations with exactly the same number of picoseconds of slack.