Stratix V Hard IP PCIe, Timing Errors

The Altera forum is maintained by users, rather than Altera directly. I'd recommend filing a Service Request with Altera and asking their advice.

I agree that its disconcerting when black-box IP does not meet timing, given that you have no idea what is wrong or how to fix it!

Your logic-lock solution seems to be a good work-around, but I'd argue that if Quartus can meet timing in that situation, then based on meeting the IP timing constraints it should have placed the logic that close together without the user having to add a logic-lock region!

Please post the response to your Service Request if you learn something useful :)

Cheers,

Dave