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Altera_Forum
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11 years ago

Stratix V Hard IP PCIe, Timing Errors

Hi, I have been building a system around the Avalon-ST version of the PCIe Hard-IP for Stratix V. Specifically I am using the Gen3x8 variety. It is happily working away and I can get data ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Well, still no idea about where the errors are coming from, but I've created a logic lock region for my application layer partition and compressed it as much as possible into on corner next to the PCIe transceivers and the errors have vanished. Problem solved I guess.