Stratix V Development Kit Notes

This is not a call for help, actually, it is just informational - for all the other numbskulls like me - Im going to take about a half hour and give you some information that you might need whilst getting your S5 design going. You obviously will get most of this from the documentation, but there's little gothca's that I hope I can fill in for you.

The very first thing you should do after unboxing, is download the Stratix V development board package. Just get the whole shebang and install it on your PC. I seem to recall, when I was installing it asked which version of Quartus II I wanted it to follow and I told it 14.0.0. I don't know what that means. But I think you need to have 12.0 installed because the Clock control/Board Test system likes Quartus 12.0 programmer in order to communicate. I'm not totally sure but if you CAN'T get communication with the board (clock manager or BTS) then install Quartus 12.0 - don't worry about all the family packages (you only need programmer).

Now you need to get communication with the board. This is best achieved with the micro USB cable provided in your Kit. Power up the board, plug in the cable, and let the drivers install. Then make sure your environment variables in Windows are pointed at the right place. Go into Control Panel > System and Security > System > Advanced System Settings > Environment Variables. From there, find QUARTUS_ROOTDIR and point it at your 12.0 root directory (for me it was E:\altera\12.0\quartus). Now you have to Reboot your system - or at least I had to. Again - I'm not sure if I could have pointed this at my 14.0 but 12 was working so I just kept it at that.

Once rebooted, start your clock manager tool that came with the Stratix V package you insalled earlier (if you did not, go do it!!!). You can find all the goodies EASILY by going to (Windows start Icon) > ALL PROGRAMS > Altera > Stratix V GX FPGA Development Kit V 12.0.0.1. There you should have instant access to the schematics, user guides, clock manager, etc.

So Start Clock Manager. You should see the program negotiating and make a connection, if not go back and keep mucking with your environment settings. Also, check your device manager, make sure you see JTAG CABLES > Altera usb blaster blah blah underneath.

So the clock manager is very important. There are hard fixed clocks on the board that you will need to know how to set up and use. On Page 31-ish of the Package reference manual, you should see a breakdown of the clocks. Its important that you see where dedicated clocks go. For example, for my design, I needed to bring in my GX clock according to the region that I was planning on sending out my GX output. Thus I had to use U38, Clk 0 - which is set up by the clock manager. So each time I boot the board, I have to fire up clock manager, and set clk0 frequency to my needs. I also had to do this for my DDR3 clock, on X4(Si570) bottom edge memory, pins J23/J24 (had to set to 125 mHZ through clock manager for me DDR3 controller reference clock).

The point is there are a lot of dedicated clocks and lines but most can be adjusted with clock manager - just make sure you select the right clocks for the regions you are using.

So getting the GX was not too much of a challenge for me, we had legacy Altera designs and I was able to set the GX up first time and get it mapped to valid pins to go out my HSMC connector. Again, I had to use a dedicated clock that already had routings to the GX I needed to use (U38, clock0).

It was DDR3 that gave me the biggest challenge. I could not find a reference design that was not a qsys design, so let me give you my tips. First of all, there's a project in the development kit subdirectories called "Golden_top". Open that bad boy with Quartus II, and compile it. Then open the Assignment editor and export the assignments as a csv file. This will give you a nice listing of pinouts of ALL the connected goodies on the board. Second, after you generate your DDR3 controller, you will integrate into your design. I'd go right away and try to compile so that Quartus can parse the design and get your pins available for pin planner. Then go in and pin plan each of your pins - just worry about locations and standards for now. As I said you can use your exported .csv file for the golden_top design, or you can go through the pain of the reference Manual or even worse - the schematic. But get your pins mapped in pin planner along with the I/O standards. NEXT open your tools > tcl Scripts. It should be pointing at your IP directory - ish. If not browse around your projects to find your DDR controller IP, and run these scripts...<your_ddr_controller_name>_p0_parameters.tcl then <your_ddr_controller_name>_p0_pin_assignments.tcl.

If you don't do that, you will get this goofy error: (due to that first script not being run yet - which will eventually set up the input/output terminations for the DDR pins)

Error (174068): Output buffer atom "Video_Memory:vid_mem|DDR3_controller:Inst_DDR3_Controller|DDR3_controller_0002:ddr3_controller_inst|DDR3_controller_p0:p0|DDR3_controller_p0_memphy:umemphy|DDR3_controller_p0_new_io_pads:uio_pads|DDR3_controller_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_stratixv:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination

and so on, so forth.

Now check your assignment editor, you should see more assignments than you put in just with the pin editor (like input/output terminations, etc).

Finally - if you don't have your clock mapped right - meaning you mapped a DDR3 reference clock wrong - you will get these errors:

Error (14566): Could not place 25 periphery component(s) due to conflicts with existing constraints (25 pin(s))

Error (175020): Illegal constraint of pin to the region (17, 129) to (19, 129): no valid locations in region

Info (14596): Information about the failing component:

Info (175028): The pin name: mem_dm[1]

Info (14597): No legal location could be found for this component out of 1 considered location(s). Reasons why each location could not be used are summarized below:

Info (175015): The I/O pad mem_dm[1] is constrained to the location PIN_J28 due to: User Location Constraints (PIN_J28)

Info (14709): The constrained I/O pad is contained within this pin

Error (175006): Could not find path between source fractional PLL and the pin

Info (175026): Source: fractional PLL Video_Memory:vid_mem|DDR3_controller:Inst_DDR3_Controller|DDR3_controller_0002:ddr3_controller_inst|DDR3_controller_pll0:pll0|pll1~FRACTIONAL_PLL

Info (175021): The fractional PLL was placed in location FRACTIONALPLL_X98_Y11_N0

Error (175022): The pin could not be placed in any location to satisfy its connectivity requirements

Info (175029): 1 location affected

Info (175029): J28

And so on, so forth...

&#8203;Those are just my tidbits so far, I'll post anything else that might help later.