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I can confirm that the USB Blaster works. It detects the device just fine and it was used to program another CPLD on the board with no issues.
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Ok.
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It also reports success upon completion -- if I pull nCE high, the programmer (via the USB Blaster) reports failure at 97%
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Sorry, its not clear what you mean here ... completion of the CPLD, or completion of the FPGA?
Do you have a development board with the same FPGA on it and a USB-Blaster II interface? You could create a design with something as simple as a JTAG-to-Avalon-MM bridge and some internal registers/ram, so that it has no I/O. You could then download that to your known-good development board to confirm that the image is good. If you then download that same image to your custom board and it does not work, you then know that the problem is related to your hardware (rather than some issue with FPGA image generation).
Random thought; I recall some issues with security modes on engineering samples (but do not recall if the issue was Stratix V related). Check the errata for your device and see if there is anything weird you have missed that might be related to this problem.
Cheers,
Dave
Honored Contributor
