Stratix V - JESD204B Lane Polarity Inversion

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Some further analysis of the sample JESD204B design (found from the Qsys IP code) when the synthesis code is generated, I have determined that in "altera_jesd204_altera_jesd204.v" there is a signal called "inst_rx_csr_lane_polarity_export" which connects "inst_rx" to "inst_phy". Now it seems that this signal has a sensible name for what I need, but has no external parametrisation - and the "inst_rx" is an instance of an encrypted IP core, so I've got no idea what it connects to internally.

Would it be possible to simply remove this wire and assign it to a constant value thereby permenantly enabling polarity inversion? If so what constant value would enable inversion (a 1 or a 0)?

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It seems like you are trying to edit the IP design file to enable the polarity inversion. I would recommend to contact Altera to seek for any workaround to avoid malfunction to the IP and your device.