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Altera_Forum's avatar
Altera_Forum
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10 years ago

Stratix V - JESD204B Lane Polarity Inversion

I am currently trying to find a way to connect an ADC dev kit to a Stratix V DSP Development Board. The ADC board uses an FMC connect, whilst Altera use the HSMC connector. As a result I will need to make an adapter board to connect the two.

Having had a brief look at the two connectors and pin assignments of both, it seems that an adapter board should be fairly simple - there are not that many pins. However, the ADC uses JESD204B which means high speed differential routing which could get tricky quickly. As it happens the ADC can work on only 2 lanes (one per channel) out of its 4 physical connections, which is our plan for an eventual board with 12 channels (there are only 12 transciever lanes spread across the two HSMC connectors). So ideally my adapter board will mimic the eventual design to aid in prototyping and firmware development. The data rate on these lanes will end up being roughly 4Gbps which is going to require very careful routing and ideally I would like to minimise passing traces through the PCB (I want to use a 4-layer design to minimise costs). It appears from the pin assignments that if the two connectors (HSMC and FMC) are placed on the same side of the board, then there will be a straight run from the RX pins on the HSMC connector and the outer edge of the FMC connector (where the ADC board routes its JESD lines) so in this regards no layer swapping would be required which is excellent. However on closer inspection it seems that it isn't as simple as first thought. While the lanes are on the correct side of the connectors, if a straight run was used, the P and N lines of each JESD pair would get swapped.

Unfortunately, the ADC itself does not support lane polarity reversal - some do, but the one selected does not. So the reversal would have to be done in the FPGA. I've been doing some reading of the Altera datasheets, and it seems that the transcievers on the Stratix V when using the hard PCS support lane polarity inversion - seemingly it is there for board design errors, but I would like to make use of it for rapid prototyping (for the final board revision we won't be using the ADC dev kit so for that we can ensure the correct lane polarity).

So the question is, before I start working on this, could someone confirm that wen using the Altera JESD204B IP core with the Stratix V (5SGSMD5K2F40C2), that it will be possible to enable lane polarity inversion, in either of the soft or hard PCS modes?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Some further analysis of the sample JESD204B design (found from the Qsys IP code) when the synthesis code is generated, I have determined that in "altera_jesd204_altera_jesd204.v" there is a signal called "inst_rx_csr_lane_polarity_export" which connects "inst_rx" to "inst_phy". Now it seems that this signal has a sensible name for what I need, but has no external parametrisation - and the "inst_rx" is an instance of an encrypted IP core, so I've got no idea what it connects to internally.

    Would it be possible to simply remove this wire and assign it to a constant value thereby permenantly enabling polarity inversion? If so what constant value would enable inversion (a 1 or a 0)?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    Some further analysis of the sample JESD204B design (found from the Qsys IP code) when the synthesis code is generated, I have determined that in "altera_jesd204_altera_jesd204.v" there is a signal called "inst_rx_csr_lane_polarity_export" which connects "inst_rx" to "inst_phy". Now it seems that this signal has a sensible name for what I need, but has no external parametrisation - and the "inst_rx" is an instance of an encrypted IP core, so I've got no idea what it connects to internally.

    Would it be possible to simply remove this wire and assign it to a constant value thereby permenantly enabling polarity inversion? If so what constant value would enable inversion (a 1 or a 0)?

    --- Quote End ---

    It seems like you are trying to edit the IP design file to enable the polarity inversion. I would recommend to contact Altera to seek for any workaround to avoid malfunction to the IP and your device.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi, did you ever get this working? Also, can you run the JESD megafunction without using a NIOS processor? Thanks, Joe