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RBach6's avatar
RBach6
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7 years ago

Stratix IVGX (EP4SGX70HF35C3) PLL+SERDES issue

Hi, I am using an eval board from Texas Instruments (TSW1400evm). I am trying to implement altpll+altlvds_rx and running into an issue. Clock pin goes into pins AA7 and AA6 which are dedicated clock...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
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7 years ago

Hello Ramakrishna ,

Today i get chance to look at the file ,

I removed your pin assignment in the editor and try to build. It complies fine ....Can you check the pin assignment by default Quartus fitting with which location to the PLL and cross verify with yours ?

Thank you ,

Regards,

Sree