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RBach6's avatar
RBach6
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7 years ago

Stratix IVGX (EP4SGX70HF35C3) PLL+SERDES issue

Hi, I am using an eval board from Texas Instruments (TSW1400evm). I am trying to implement altpll+altlvds_rx and running into an issue. Clock pin goes into pins AA7 and AA6 which are dedicated clock...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

13.1 is older version ....I will try and let you know :)

Thank you ,

Regards,

Sree