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RBach6's avatar
RBach6
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7 years ago

Stratix IVGX (EP4SGX70HF35C3) PLL+SERDES issue

Hi, I am using an eval board from Texas Instruments (TSW1400evm). I am trying to implement altpll+altlvds_rx and running into an issue. Clock pin goes into pins AA7 and AA6 which are dedicated clock...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
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7 years ago

Hello Ramakrishna,

Sorry , I didnt get notification that you replied and I am just cross verifying something else i came across your post .

Can I know did you find a way to fix this issue ? if not , Can you send the files and I will look at now ?

Thank you ,

Regards,

Sree

  • RBach6's avatar
    RBach6
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    7 years ago

    Hi Sree,

    I am attaching the code along with this replay. I was using Quartus 13.1 to compile the code. Please let me know, if you find something

    Thanks,

    Ramakrishna