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RBach6's avatar
RBach6
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7 years ago

Stratix IVGX (EP4SGX70HF35C3) PLL+SERDES issue

Hi, I am using an eval board from Texas Instruments (TSW1400evm). I am trying to implement altpll+altlvds_rx and running into an issue. Clock pin goes into pins AA7 and AA6 which are dedicated clock...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
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7 years ago

Hello Ramakrishna ,

If you plan to use the non -DPA mode , PLL which is driving the non-DPA mode SERDES should be compensated . LVDS Compensation option will be there in the PLL IP setting .In Non-DPA mode you have to make sure DATA and CLOCK compensate for the SKEW.

can you kindly refer below link document ? which contain full insight of LVDS SERDES IP. " Table 20 "

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf

I thought you were just converting Verilog to VHDL from the TI example design .

Thank you ,

Regards,

Sree

  • RBach6's avatar
    RBach6
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    7 years ago

    Hi Sree,

    I selected the option of "In source-synchronous compensation Mode" and I still get the same error. I tried all possible options and I still get the same error. I can send my code, if it helps looking into this issue. Please let me know

    Thanks,

    Ramakrishna