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RBach6's avatar
RBach6
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7 years ago

Stratix IVGX (EP4SGX70HF35C3) PLL+SERDES issue

Hi, I am using an eval board from Texas Instruments (TSW1400evm). I am trying to implement altpll+altlvds_rx and running into an issue. Clock pin goes into pins AA7 and AA6 which are dedicated clock...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
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7 years ago
Hello Ramakrishna , Thank you for the question, Apologize for delayed response. I have couple of questions .. Can I assume you didnt change the any pin mapping in the design from the TI evm ? but EVM schematic looks like not using the PLL_B1. Also from the TI EVM desgn using the Top PLL not right or bottom can you give me more detail about difference between your design and TIevm ..from the pin mappin PLL inst is not looks same. Kindly correct me if iam wrong ? Thank you, Regards, Sree