Forum Discussion
Occasional ContributorStratix IV Max Clock Input Voltage
Hi
We have an existing board containing a EP4SE360F35I3 (F1152 PACKAGE).
I am trying to determine the maximum input Voltage that can be placed on a dedicated clock input pin (single ended). Specifically CLK8P and CLK10P.
CLK8P is bank 5C which is at 2.5V, CLK10P is bank 6C which is at 2.5V.
From the documentation a dedicated clock input pin, in single ended mode, complies to LVPECL, which is quoted elsewhere as having a maximum input Voltage of 2.625V.
However, I am confused by the 3.3V compliance/support for the I/O pins.
Ideally we would like to use a 3V clock signal on these clock pins and any advice would be much appreciated.
Best regards
Simon
1 Reply
Rahul_S_Intel1Frequent Contributor
Hi Simon,
The LVPECL VCCIO is given as 2.65 V ( page no:22 of the below document) , not the input voltage to the LVPECL standard
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-iv/stx4_5v4.pdf
The LVPECL standard is been characterized in 2.5V IO standard , not in 3 V IO standard.
So from Intel , it is not recommended to connect t o 3V IO standard to LVPECL.
