Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Stratix IV JTAG configuration issue

Hi,

We are facing an issue with FPGA programming. We have a FPGA sof file for Stratix IV which has lesser logic (10-20%) and used for testing. We are able to program this file without any issue multiple times.

But when we put FPGA SOF with more logic (70%), configuration is not happening. The Quartus II programmer says that Configuration is done successfully. But we see that the logic is not working as well as the Config_Done pin of FPGA is not going high. In that logic, we are driving a LED with an output pin. When the configuration is 100% complete, the LED just comes up and then switches off momentarily. What could be the problem. Please help.

Thanks & Regards,

Ram.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Could it be a power supply problem? If your second design uses more power and the decoupling is insufficient, it could cause the FPGA to reset just after configuration.