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Altera_Forum
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15 years ago

Stratix IV JTAG configuration issue

Hi, We are facing an issue with FPGA programming. We have a FPGA sof file for Stratix IV which has lesser logic (10-20%) and used for testing. We are able to program this file without any...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Could it be a power supply problem? If your second design uses more power and the decoupling is insufficient, it could cause the FPGA to reset just after configuration.