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joseph_wu's avatar
joseph_wu
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4 years ago

Stratix IV GX 230 DDR2 Example Design Issue (EP4SGX230KF40C2)

Hi all, I was trying to use the DDR2 controller with UniPHY IP with the following steps, Set the parameters for the memory controller (as attached) According to the datasheet of the DDR2 pr...
AdzimZM_Altera's avatar
AdzimZM_Altera
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4 years ago

Hi Joseph,


Thanks for sharing the design file.


Have you tried to simulate this example design?


But I think that the issue is related to the hardware.

  • Can you check the clock frequency on the board?
  • Make sure all connections are right.
  • If possible, can you test with different memory and other Stratix IV board?


Thanks,

Adzim



joseph_wu's avatar
joseph_wu
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4 years ago

Hi Adzim,

Yes, I have tried simulating the design and the waveform seems normal.

As for the hardware,

  • I have tried programming the FPGA with 400 MHz (highest acceptable frequency for DDR2) and 300 MHz, but both failed
  • Could you please provide the connection references for the example design for me to check?
  • I could not test with different memory and other Stratix IV board for now

Thank you!

Joseph