Stratix III JTAG/POR Issue

helac,

Are you sure the board is functioning as expected? For my board, the thermal problem seemed to be caused a switching power supply powering high current components (that should have been off) using a buck/boost supply that wasn't boosting -- that generated alot of heat from switching losses and powering ICs that had noise for data.

I haven't done a temperature measurement, but it got hot enough so that you could only touch the FPGA for a few seconds before it became uncomfortable. Seems like your problem might be a little different than mine -- how fast are you clocking your design? Perhaps you may want to add a heatsink to the FPGA. It's certainly conceivable that heat caused the JTAG interface to to malfunction/shutdown/stop working, but I would try waiting until the board is cool, and try it again (or try programming using AS if possible).

Regarding the state of the I/O lines, they were definitely sourcing current (there were some LEDs on I/O lines that were partially lit). I remember reading somewhere (maybe in Quartus, or the documentation for Quartus) that the default configuration state of the FPGA I/O pins is tristated, and weakly high. I could have avoided the issue by programming the serial config flash on my board, but my MSEL pins were not configured properly, hence my original dilemma.

Alfred