Stratix III JTAG/POR Issue

Ok, I thought about my last post a bit more (took a walk) and remembered that the Stratix III I/O pins are tri-stated and weakly pulled up by default. I started thinking about how the two boards responded differently and remembered there were some problems with the layout which we discovered using the "bad" board and then fixed on both the "bad" and "good" boards (maybe the "bad" board's FPGA got damaged while troubleshooting).

Here's my diagnosis: I think the I/O lines are enabling other parts of the board that are not supposed to be on yet, causing the switching power supplies to work really hard to power those components that are processing bogus data (there are some RF/mixer components on the board, which also generate alot of heat), which makes the board really hot (thermal design is probably not as good as it could have been) and possibly causes the FPGA to either shutdown or not work properly.

The end result is a "bad" board that never works, and a "good" board that can JTAG for a minute before getting too hot. If you program it before then, everything is copacetic. Of course the Active Serial configuration problem doesn't help matters, but I think the answer to that is to drill out the GND via for the MSEL0 line and tie it high, like it should have been. In any case, I've got one board that can reliably JTAG, so I'm happy.

Thanks to Jerry and anyone who took a look at the thread and gave it some thought.