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Altera_Forum
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16 years ago

Stratix III JTAG/POR Issue

Greetings, I'm working with a Stratix III FPGA (EPSL70F484) on a custom PCB configured in a JTAG / AS configuration with a EPSC16 and ran into a nasty problem. When I first powered up the board...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Yes, it is a multi-voltage design. I've attached a screenshot of the power supply portion of the board -- as you can see we're using several different IO voltages, but with respect to the JTAG interface, we're using 3.0V on VCCPGM and 2.5V on VCCPD1C (the bank from which the JTAG interface is powered, according to the handbook).

From what I recall in the handbook, this is all acceptable (although the 3.0V on VCCPD6A and VCCPD6C makes me nervous) but here's the weird part -- I tested the other prototype board and the JTAG chain enumerated (after not enumerating before)! This would seem to eliminate the power/JTAG interface design as the direct problem (unless the power configuration "breaks" the FPGA after a certain amount of time).

Now I'm leaning back towards a temperature related problem, but there are still some questions that temperature alone cannot answer (why are the config pins not in the expected state, why are the I/O lines sourcing/sinking current when they should be high impedance) -- has anyone seen this kind of behavior before?