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Altera_Forum
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16 years ago

Stratix III EP3SL340c3 Diffrential IO data rate

Hi I have been working on DE3 board with the above mentioned FPGA for some months now. I am trying to deserialize 8 LVDS channels from an ADC. each channel is 12 bits and ADC can work upto 50 Mega...
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Altera_Forum
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16 years ago

Thanks alot Rysc for the constraints guidance. Helped a lot. Now i have designed the deserializer with an altddio_in first and shift registers afterwords. Simulation shows the right results for the first time using TimeQuest timing analyzer. I will try this out on the DE3 in university tomorrow as I am at home now. Hopefully, it will work out or i'll be troubling you guys again :P

Thanks again to both Rysc and FvM for your help.