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Altera_Forum
Honored Contributor
16 years agoPlease be patient, you asked your question during the holidays, and not everyone read the forum during new year's eve ;)
I'm not aware of any remote update example without a CPU. In my opinion checking if a valid application image is present in the flash and reconfigure the FPGA from that is easier to do with a CPU than with just HDL. You can support both JTAG and active serial configuration in the same design. The FPGA will load its configuration from the flash first, but you can also upload your image through JTAG. You can also access the flash memory from the JTAG interface by using a SFL (Serial Flash Loader).