Altera_Forum
Honored Contributor
17 years agostratix II EP2S60
I am just starting with FPGA, and i need help if its possible.
I have a board "stratix II EP2S60" and I want download the file "nios.sof" via Jtag Uart, but I have an error, I receive the message: Error: Can't communicate with device. Device will stop functioning when it reaches its non-tethered mode timeout limit. after compilation, I receive the message: Warning: Using design file cpu_jtag_debug_module.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project + the file generated is "nios_time_limited.sof"?????? Thanks