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Altera_Forum's avatar
Altera_Forum
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13 years ago

Stratix II configuration problems

Hello,

I'm using Quartus-II V8.1 and would prefer to stay with that version if all

possible because of legacy systems. I have a custom board that uses a

Stratix II (EP2SF484C3) and a EPCS64 configuration device.

There are two 10pin headers for a JTAG and Active Serial (AS) interface.

Downloading logic to the FPGA through the JTAG interface has no

problems. For AS mode, I check the 'program' and 'verify' boxes. It

appears to have programmed the EPCS64. All messages are green

and display no errors.

After programming in AS mode, I disconnected the USB blaster and power

cycled the board. The FPGA does not seem to have the logic design. I

have on-board LEDs that display a specific pattern (0x55) that is

displayed after downloading through the JTAG and isn't after

programming the EPCS64. All outputs are high.

For programming the EPCS64, I used the design as shown in the "Stratix II

Device Handbook, Volume II (page 7-44);" however, I inadverently

connected both nCS and nCSO together and are tied through a 10K

resistor to 3.3V. Would that cause any problems?

I checked the voltages on the 10pin header used for AS mode without

the USB blaster cable. Is 2.3V correct for pins such as nCS (pin 8)? What

should the voltages be?

In general, what else should I be looking at? Any help is appreciated.

Thanks in advance,

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    I inadverently

    connected both nCS and nCSO together and are tied through a 10K

    resistor to 3.3V. Would that cause any problems?

    --- Quote End ---

    Perhaps. nCS should be held low. This 'selects' the first device in the JTAG chain. When that first device finishes configuration, then it asserts nCSO to the next device.

    The question is whether nCSO is tri-stated by the FPGA, or driven high. You'll have to look that up in the data sheet. If it is driven high, then nCS will be high at power-on, and your device cannot configure. Actually, since you have a pull-up, it will be high regardless. That would be a problem.

    --- Quote Start ---

    I checked the voltages on the 10pin header used for AS mode without

    the USB blaster cable. Is 2.3V correct for pins such as nCS (pin 8)?

    --- Quote End ---

    I would have expected 0V.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Update:

    The problem was two fold. One, I mistakenly connected the nCS pin instead of the nCSO pin (D11). I corrected this by cutting the nCS trace and soldering on a jumper from nCSO to pin 8 on the Active Serial 10 pin header. Also I added a 10K pull-up resistor. Unfortunately, after doing so, it still didn't work. Second, one of our Tech's here had a good idea of placing weight on the FPGA. After do this, it fired up properly 100% of the time. There must have been a problem with bonding the FPGA to the board (gold).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    one of our Tech's here had a good idea of placing weight on the FPGA. After do this, it fired up properly 100% of the time. There must have been a problem with bonding the FPGA to the board (gold).

    --- Quote End ---

    For a fee, a commercial assembly house can perform an X-ray of the board through horizontal layers. Its like a hospital CT scan for a human. The X-ray resolution is fine enough to produce a slice at the PCB surface, the middle of the BGA ball, and the top of the BGA ball (at the package). Image recognition software is then used to check that each BGA ball is attached correctly.

    If you consider the lost time debugging assembly issues, the cost of the X-ray inspection is not bad.

    Cheers,

    Dave