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Altera_Forum's avatar
Altera_Forum
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7 years ago

Stratix II cannot config with JTAG or AS

Hello everyone,

There is a very strange problem with the EP2S60F484:

I have a product base on EP2S60F484, and it had be producted for over a year.

But recently a problem appear: All the products with the FPGA whose batch No is 1713 can't config successfully and JTAG also failed.

Quartus show the info Config_done Pin can't go high.

I also measured voltage of config_done pin is 0V.

nConfig is high.

I changed old batch FPGA and it can work well.

I wonder is there any difference between the new batch and old batch of the FPGA(EP2S60F484)??

thanks!!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Hi,

    1. Have loaded .sof file via JTAG configuration for batch No is 1713?

    If the .sof file can be configured via JTAG successfully. Thus it is not a power issue since JTAG configuration is successful. If the JTAG configuration with .sof file failed, thus it is a power issue.

    Monitor the nStatus signal again.

    1. The time when the nSTATUS goes low. Does the nSTATUS signal low from the beginning right after power up? Or during in the middle of configuration process, the nSTATUS from high (logic 1) then suddenly goes low (logic 0)?

    a. If the nSTATUS is low from the beginning right after power-up, then even JTAG configuration with the .sof file would fail.

    b. If the nSTATUS from high (logic 1) then suddenly goes low (logic 0) during the middle configuration process, then either due bitstream corruption or power issue.

    Also, check each power supply voltage level requirement from the datasheet.

    Troubleshooting Guide:https://www.altera.com/support/support-resources/support-centers/devices/cfg-index/fpga-configuration-troubleshooter.html

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Thank you for reply,

    I had tried to load .sof file via JTAG, but failed. Quartus showed the loading process stop at 89%, config_done can't go high.

    I also download the latest version of the Quartus II and regenerate the programming file. Also failed.

    and here is the nStatus signal in JTAG mode.

    The blue is nStatus signal, and the yellow is nConfig signal.

    nStatus goes low every 2.4ms

    http://i4.bvimg.com/644088/19e3341e6e6c38d3.jpg

    this pic show nStatus signal and nCSO signal in AS mode.

    The blue is nStatus signal, and the yellow is nCSO signal.

    http://i4.bvimg.com/644088/d87b464d477fd1dd.jpg

    I'm sure the bitstream is ok because it work well in the old batch No EP2S60F484.

    I also measure the ripple voltage and it is in the normal range.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Hi,

    It is a power issue.

    Kindly check hardware components like dc/dc converters and passive components on power plane.

    Refer POR circuitry requirements.

    Also ensures that all eight I/O bank VCCIO voltages, VCCPD voltage, as well as the logic array VCCINT voltage, reach an acceptable level before the configuration is triggered.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)