MIT_R_D
Occasional Contributor
Occasional ContributorStratix 10 SX SOC DVK: Seeing (Detected)Errors on HPS DDR during testing by BTS Example Project
We brought new S10 SX SoC DVK. We started with initial Board testing with BTS. we are able to program GPIO, FMCA & FMCB sof and tested the functionality. We are able to test GPIO and SERDES and it...
Reason for Failure: HPS DDR Parameters were different in example design and BTS HPS_DDR Example Design. May be deferent DDR speed grade used in old and new DVK
If anyone face this issue with latest S10 SX DVK.
Please change HPS DDR Parameters like below(old speed bin - 2400 and new speed bin - 2666)
U can also download above GHRD project and reverify. above GHRD having proper HPS DDR parameter settings
