Stratix 10 hold time doubt, low resource occupation FPGA

I've never heard of such a thing either.

Hold time violations occur because of "too fast" signaling, causing signals to not be held long enough after a long edge. A mostly empty device gives the Fitter basically an infinite number of possibilities for placing and routing a small design that will meet timing as long as correct timing constraints are created. The Fitter will follow the constraints to meet timing, not just put stuff close together because it can.