Stratix 10 generating square wave on L-Tile Transceiver Native PHY

Hi,

As I understand it, you have some inquiries related to the tx local clock divider.

For your information, the TX local clock divider is not dividing the serial output data rate. Instead, it is dividing the serial clock fed from the TX PLL. This allows you to use a single TX PLL to drive different channels running at data rate in division of 2 from the base. For example, using a PLL running for 10000Mbps, you can also use the same PLL to drive channels at 5000Mbps (division of 2), 2500Mbps (division of 4) and 1250Mbps (division of 8). This helps to save the PLL resources.

Please let me know if there is any confusion with my explanation. Thank you.